基于ANSYS 的DDR4 SDRAM 信号完整性仿真方法研究
Signal Integrity Simulation Method of DDR4 SDRAM System Based on ANSYS
  
DOI:
中文关键词:  双倍数据速率同步动态随机存取存储器,信号完整性,同步开关噪声
英文关键词:double data rate synchronous dynamic random access memory (DDR SDRAM), signal integrity, synchronous switching noise (SSN)
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作者单位
汪振民,张亚兵,陈付锁 中国电子科技集团公司第十四研究所, 南京 210039 
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中文摘要:
      半导体技术快速发展,双倍数据速率同步动态随机存取存储器(Double Data Rata Synchronous Dynamic Random Access Memory, DDR SDRAM)的信号完整性问题已成为设计难点。文中提出了一种基于ANSYS 软 件和IBIS 5. 0 模型的DDR4 SDRAM 信号完整性仿真方法。利用IBIS 5. 0 模型中增加的复合电流(Composite Current) 、同步开关输出电流等数据,对DDR4 SDRAM 高速电路板的信号完整性进行更准确的仿真分析。仿真结果 表明:高速信号在经过印制板走线和器件封装后,信号摆幅和眼图都有明显恶化;在仿真电路的电源上增加去耦 电容后,信号抖动和收发端同步开关噪声(Synchronous Switching Noise, SSN)都得到明显改善;在不加去耦电容的 情况下,将输入信号由PRBS 码换成DBI 信号,接收端的同步开关噪声有所改善,器件功耗可以降为原来的一半。
英文摘要:
      With the development of semi-conductor technology, the signal integrity of DDR SDRAM is becoming a big challenge for designers. This paper proposes a signal integrity simulation method of DDR4 SDRAM based on ANSYS and IBIS 5. 0 Model. The signal integrity of high speed circuit board with DDR4 SDRAM is simulated more accurately by using the data of composite current and synchronous switching output current added in IBIS 5. 0 Model. The simulation results demonstrate that the amplitude and eye diagram of high speed signals are deteriorated obviously after signals go through PCB wires and packages. After adding decoupling capacitor to the power supply of the simulation circuit, jitter and SSN of the transmitter and receiver are significantly improved. When the input signal is changed from PRBS code to DBI signal without decoupling capacitor, SSN of the receiver is improved, and the power consumption of the device can be reduced to half of the original.
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